VHDL

Introduction

VHDL (VHSIC hardware description language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits.

VHDL is commonly used to write text models that describe a logic circuit. Such a model is processed by a synthesis program. A simulation program is used to test the logic design using simulation models to represent the logic circuits that interface to the design. This collection of simulation models is commonly called a testbench.

VHDL has constructs to handle the parallelism inherent in hardware designs. VHDL is strongly typed and is not case sensitive.

A final point is that when a VHDL model is translated into the "gates and wires" that are mapped onto a programmable logic device such as a CPLD or FPGA, then it is the actual hardware being configured, rather than the VHDL code being "executed" as if on some form of a processor chip.

As last remark I want to thank Corthay Francois for his VHDL Summary and HTML files.

PDF

• ESA VHDL Modelling Guide
• Synth Works Fixed & Float
• Synth Works Math Tricks
• Synth Works Verification
• Synth Works VHDL 2008 End of Verbosity
• Short Guide CoF
• EPFL VHDL Script

Links

• Wikibook VHDL Programmable Logic
• Wikibook VHDL for FPGA Design
• Wikibook VHDL
• VHDL Guide
• Compact Summary of VHDL
• Open cores - Free VHDL/Verilog IP's
• VHDL Guru Blog
• Synth Works

Contents

• Guidelines
• Syntax
• Attributes
• Conversion
• File
• Libraries
• Examples
• Testbench
• Time
• OSVVM
• Simulation
• Synthesis
• Intel SDC
  • SDC Constraints
  • Theory
  • Usage
• Xilinx UCF